(China (Mainland))
Product Summary
THC63LVD104A converts the LVDS data streams back
into 35bits of CMOS/TTL data with rising edge or fall-
ing edge clock for convenient with a variety of LCD
panel controllers.At a transmit clock frequency of
90MHz, 30bits of RGB data and 5bits of timing and
control data (HSYNC,VSYNC,DE,CNTL1,CNTL2)
are transmitted at an effective rate of 630Mbps per
LVDS channel.Using a 90MHz clock, the data through-
put is 394Mbytes per second.
Features
Wide dot clock range: 8-90MHz suited for NTSC,
VGA, SVGA, XGA, and WXGA
PLL requires no external components
50% output clock duty cycle
TTL clock edge programmable
Power down mode
Low power single 3.3V CMOS design
64pin TQFP
Backward compatible with THC63LVDF64x
(18bits) / F84x(24bits)
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||
|---|---|---|---|---|---|---|---|---|---|---|
 |
 THC63LVD104A |
Other |
|
Data Sheet |
Negotiable |
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| Image | Part No | Mfg | Description | |
Pricing (USD) |
Quantity | ||||
|
THC63LVD103 |
Other |
|
Data Sheet |
Negotiable |
|
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|
THC63LVD104A |
Other |
|
Data Sheet |
Negotiable |
|
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|
THC63LVD104S |
Other |
|
Data Sheet |
Negotiable |
|
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|
THC63LVD823 |
Other |
|
Data Sheet |
Negotiable |
|
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|
THC63LVD824 |
Other |
|
Data Sheet |
Negotiable |
|
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|
THC63LVDF64A |
Other |
|
Data Sheet |
Negotiable |
|
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